The present disclosure relates to a circuit configured to stabilize a reference voltage. In particular, the present disclosure relates to a reference voltage stabilizer circuit suitable for an AD converter.
AD converters have been broadly used in various fields of signal processing, and the conversion accuracy thereof is an important indicator for performance. In general, the AD converters perform AD conversion by comparing an input signal with a reference voltage. For such a reason, it is significantly important for maintenance of a high conversion accuracy to maintain the reference voltage stable with good accuracy. Depending on applications, lowering of the AD conversion accuracy often occurs due to superimposition of mV-order noise on the reference voltage. Thus, in order not to swing the reference voltage due to, e.g., disturbance noise or self-noise generated from the AD converter itself, it is important to stabilize the reference voltage.
In recent years, increasing attention has been given to successive approximation AD converters because of a high power efficiency thereof. FIG. 10 illustrates a configuration of a typical successive approximation AD converter. A successive approximation AD converter 100 includes a capacitor DAC 102 including a capacitor array for which capacitor values (1C, 4C, 8C, . . . , 512C illustrated in the figure) are weighted according to a binary ratio, a comparator 104 configured to compare an analog input voltage IN with a voltage generated by the capacitor DAC 102, a latch circuit 106 configured to store a comparison result, and a DAC controller 108 configured to control the capacitor DAC 102 based on a signal output from the latch circuit 106. In the capacitor DAC 102, first ends of the capacitor array are commonly connected to the analog input voltage IN, and each of second ends of the capacitor array is independently connected to one of reference voltages VREFH, VREFL (VREFH>VREFL) according to a multiple-bit control signal output from the DAC controller 108.
Operation of the successive approximation AD converter 100 is as follows. First, the analog input voltage IN is sampled at the capacitor DAC 102 in the state in which an MSB of a control signal is “1” and the other bits are “0.” Then, based on a comparison result of the comparator 104, the DAC controller 108 successively determines, for each clock, the bits of the control signal one by one in the order from the MSB to lower bits. At this point, a signal generated in such a manner that a signal output from the latch circuit 106 is serial-parallel converted is an AD conversion result of the sampled analog input voltage IN.
If mV-order noise is superimposed on VREFH-VREFL at timing at which the comparator 104 is operated at each clock, an AD conversion error occurs. Moreover, the charge of the reference voltage VREFH, VREFL is consumed at timing at which a connection state of the second ends of the capacitor array is changed after the comparator 104 is operated. This causes self-noise of the AD converter.
Conventionally, it has been often the case that bypass capacitors (capacitive elements) are provided inside and outside an integrated circuit to remove noise superimposed on a reference voltage. Referring to, e.g., FIG. 11, in the configuration in which voltages supplied from an external power supply 200 are received by I/O pins P1, P2 and are then supplied to the AD converter 100 through signal lines L1, L2 as the reference voltages VREFH, VREFL, an external bypass capacitor (capacitive element 202) may be provided between the I/O pins P1, P2 outside an integrated circuit 300, and an internal bypass capacitor (capacitive element 203) may be provided between the signal lines L1, L2 inside the integrated circuit 300. However, due to an influence of a parasitic inductance 204 of a package of the integrated circuit 300, the external bypass capacitor becomes less effective around a frequency of 100 MHz or more. As a result, the external bypass capacitor no longer contributes to reduction in impedance of the signal line. If the capacitance of the internal bypass capacitor is increased in order to compensate for such a state, ringing of noise superimposed on the reference voltage occurs due to resonance with the parasitic inductance 204, and, as a result, it is difficult to reduce swing of the reference voltage. In fact, in order to obtain an about 10-bit AD conversion accuracy, it is necessary to provide an nF-order internal bypass capacitor to reduce self-noise of the AD converter 100. However, it is unrealistic to provide such a large capacitive element inside an integrated circuit.
Instead of the internal bypass capacitor, a buffer or an active bypass circuit (hereinafter collectively referred to as a “buffer etc.”) may be provided inside an integrated circuit to reduce the impedance of a signal line. For example, in an example illustrated in FIG. 12, an active bypass circuit 206 is provided inside an integrated circuit 300 (see, e.g., U.S. Pat. No. 5,049,764). In this case, the response speed of the buffer etc., i.e., how quickly the buffer etc. responds to noise and removes such noise, is an important parameter. Since the response speed is limited, the buffer etc. cannot respond to instantaneous noise faster than the response speed of the butter etc. However, if time permits, the reference voltage can be changed back to an initial value.
Clock synchronization type discrete signal processing systems such as pipeline AD converters and successive approximation AD converters are characterized in that no influence is provided on an AD conversion accuracy as long as noise is sufficiently suppressed at the moment of AD conversion. Thus, even when self-noise is generated upon AD conversion, if settling of a reference voltage to a normal value can be performed by the moment of subsequent AD conversion, no problem arises. For such a reason, the buffer etc. can be effective measures against self-noise. However, if a conversion rate increases, it is, even with the high-power large-area buffer etc., difficult to perform settling within a required time. Moreover, a parasitic inductance of a package of an integrated circuit causes ringing of the output of the buffer etc., and further delays settling. Further, in the case of disturbance noise, timing at which noise comes in is unexpectable, and therefore it is necessary to instantaneously reduce noise to an acceptable level or less. For disturbance noise, it is necessary to use some abilities of a capacitive element which is capable of instantaneously responding.
Both of the internal bypass capacitor and the buffer etc. may be combined together. However, such a case provides a trade-off between reduction in disturbance noise and reduction in self-noise. Reduction in disturbance noise by increasing the capacitance of the internal bypass capacitor results in a delay in response of the buffer etc. and a delay in settling against self-noise. Needless to say, if an nF-order capacitive element is provided inside an integrated circuit, self-noise can be reduced only by such a capacitive element. However, this is unrealistic as described above. On the other hand, even if the response of the buffer etc. is improved by decreasing the capacitance of the internal bypass capacitor, a disturbance noise reduction effect is reduced. If disturbance noise is input right before the timing of AD conversion, settling cannot be performed, resulting in occurrence of an AD conversion error. In particular, in the case where a signal line for reference voltage is shared by a plurality of AD converters in, e.g., an interleaved AD converter, self-noise of a certain AD converter enters another AD converter as disturbance noise, resulting in a more serious problem.
FIG. 13 illustrates a configuration of a typical interleaved AD converter (hereinafter referred to as an “interleaved ADC”). In the interleaved ADC, each of signal lines L1, L2 is connected to four AD converters 100, and reference voltages VREFH, VREFL are shared by the AD converters 100. The reference voltages VREFH, VREFL are input respectively to I/O pins P1, P2 from an external power supply 200. If an internal power supply is provided, an external bypass capacity (capacitive element 202) may be additionally provided. Moreover, in the interleaved ADC, an internal bypass capacitor (capacitive element 203) is provided to reduce noise. Suppose that the AD conversion performance of the AD converter 100 is 10 bits and 50 MHz. The AD conversion performance of the interleaved ADC is equivalent to 10 bits and 200 MHz.
In comparison with a pipeline AD converter (hereinafter referred to as a “pipeline ADC”) having the same performance as that of the interleaved ADC illustrated in FIG. 13, the interleaved ADC can be designed with power and an area much less than those of the pipeline ADC. On the other hand, even if the interleaved ADC and the pipeline ADC have the same conversion rate and conversion accuracy, a much higher accuracy is required for the reference voltages of the interleaved ADC, and a reference voltage circuit used for the pipeline ADC is not applicable to the interleaved ADC. This is because of the following reasons. In the pipeline ADC, the frequency of self-noise swinging a reference voltage is 200 HMz. On the other hand, in the interleaved ADC, each of the AD converters 100 performs a sampling operation at 50 MHz. However, since the configuration in which bits are successively compared one by one at each clock is employed, the internal clock of the interleaved ADC comes close to 1 GHz. Thus, if self-noise is superimposed on the reference voltage, it is necessary to perform settling to change the reference voltage back to an initial value within a short time of 1 ns. Moreover, in the interleaved ADC, self-noise of a certain AD converter 100 becomes disturbance noise for another AD converter 100. Since the self-noise of the certain AD converter 100 directly swings the reference voltage, the level of the self-noise is as high as the level of self-noise of the another AD converter 100. In addition, the self-noise of the certain AD converter 100 is input at timing different from that of the self-noise of the another AD converter 100. In order to perform settling by a buffer etc., settling should be performed within an unrealistic time, e.g., several hundred ps which is much more shorter than a time for self-noise in the case where a single AD converter 100 is provided. Otherwise, noise is input at timing of subsequent AD conversion, resulting in an AD conversion error.
It is necessary to supply a stable reference voltage not only to AD converters but also to various signal processing circuits. An extremely-stable reference voltage is required for successive approximation AD converters, in particular interleaved successive approximation AD converters, or parallelized AD converters. However, high-speed high-accuracy AD conversion cannot be ensured by stabilization of a reference voltage using conventional capacitive elements or buffers etc. Moreover, a combination of the capacitive elements and the buffers etc. provides a trade-off between reduction in disturbance noise and reduction in self-noise.
Therefore, there is a need for a reference voltage stabilizer circuit which is capable of maintaining a stable reference voltage against disturbance noise or self-noise of an internal circuit.